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DDR-SDRAM
- 本应用指南描述了在 Virtex™ -4 XC4VLX25 FF668 -10C 器件中实现的 DDR SDRAM 控制器。该实现运用了直接时钟控制技术来实现数据采集,并采用自动校准电路来调整数据线上的延迟。-This application note describes a Virtex ™ -4 XC4VLX25 FF668-10C to implement the DDR SDRAM device controller. The clock control to ach
mictor20110113
- ddr控制参考代码,串口通信可以基于此进行二次开发,fpga参考设计,对ddr设计开发有一定的帮助-ddr controller ref code
model
- 用vhdl写的 ddr sdram 控制器,数据位可以修改。在quartus2下仿真通过-With written ddr sdram controller vhdl
DDR-SDRAM
- DDR SDRAM的设计,包括DDR SDRAM控制器,以及Modelsim仿真-The design of DDR SDRAM, DDR SDRAM controller, and Modelsim simulation
DDR-SDRAM
- ddr sdram 控制器的源代码,内有vhdl和verilog。-DDR SDRAM controller
treff-ddr-sdrh
- 本程序源码是DDR SDRAM控制器的VHDL程序源源码,由ALTERA 提供 -The program source code is DDR SDRAM controller VHDL source source code provided by ALTERA
ddr_verilog
- DDR控制器的VERILOG代码;状态机;读写;刷新等操作-ddr controller,verilog
bl-8-gai-add24
- 迸发长度为8的DDR控制器,实现数据的读写,使用赛灵思的V2板子就行验证-Burst length 8 DDR controller, read and write data, and on line verification using Xilinx V2 board
DDR-SDRAM-controller-verilog-code
- DDR SDRAM控制器verilog代码及中文说明文档-DDR SDRAM controller verilog code and documentation
ddr-sdram-control
- ddr sdram控制器的设计与验证,提供了一种极为可靠且简易的控制器设计方案。-DDR SDRAM controller design and verification, providing an extremely reliable and simple controller design.
ddr_kongzhiqi
- fpga上用verilog HDL实现的ddr控制器,简单易懂,适合新手参考-FPGA on the use the verilog HDL implementation of the DDR controller, easy to understand, suitable for novice reference
DDRController
- DDR3控制器,用于FPGA内部对DDR进行操作,利用Avlone总线进行对接-DDR controller
xilinx_ddr_verilog
- xilinx赛灵思的DDR控制器源码(包括仿真与说明文档),DDR为mt46v4m16。-Xilinx DDR controller source code (including simulation and documentation), DDR is mt46v4m16.
altera_ddr_verilog
- altera的DDR控制器源码(包括仿真与说明文档),DDR为mt46v4m16,Verilog-The DDR controller source of altera (including simulation and documentation), DDR is mt46v4m16, Verilog
lattice_ddr_verilog-for-orca4
- 莱迪思的DDR控制器源码(包括仿真与说明文档),DDR为MT46V16M8,Verilog-The DDR controller source of Lattice (including simulation and documentation), DDR is MT46V16M8, Verilog
mem_interface_top_ddr_controller_0
- 在 Virtex™ -4 XC4VLX25 FF668 -10C 器件中实现的 DDR SDRAM 控制器。-DDR controller
DDR-SDRAM-Controller
- DDR SDRAM控制器verilog代码及中文说明文档-DDR SDRAM Controller Using Virtex-5 FPGA Devices
ddr
- ddr2控制器设计,适用于xilinx fpga,内含IP软核 -ddr2 controller design for xilinx fpga, embedded IP soft core
ddr_controller
- 完整的DDR控制器设计,包含代码、仿真环境、FPGA综合网表等-full DDR controller ip,include rtl code,simulation environment and testbench, fpga synthesis netlist,etc.
DDR_MO
- 使用verilog语言实现简单的DDR SDRAM控制器(Using Verilog language to achieve a simple DDR SDRAM controller)